december 2001 2001 fairchild semiconductor corporation fdc6332c rev c1 (w) FDG6332C 20v n & p-channel powertrench mosfets general description the n & p-channel mosfets are produced using fairchild semiconductor?s advanced powertrench process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. these devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the bigger more expensive tssop-8 and ssop-6 packages are impractical. applications dc/dc converter load switch lcd display inverter features q1 0.7 a, 20v. r ds(on) = 300 m w @ v gs = 4.5 v r ds(on) = 400 m w @ v gs = 2.5 v q2 ?0.6 a, ?20v. r ds(on) = 420 m w @ v gs = ?4.5 v r ds(on) = 630 m w @ v gs = ?2.5 v low gate charge high performance trench technology for extremely low r ds(on) sc70-6 package: small footprint (51% smaller than ssot-6); low profile (1mm thick) s g d d g s pin 1 sc70-6 complementary 6 5 4 3 2 1 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter q1 q2 units v dss drain-source voltage 20 ?20 v v gss gate-source voltage 12 12 v i d drain current ? continuous (note 1) 0.7 ?0.6 a ? pulsed 2.1 ?2 p d power dissipation for single operation (note 1) 0.3 w t j , t stg operating and storage junction temperature range ?55 to +150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1) 415 c/w package marking and ordering information device marking device reel size tape width quantity .32 fdc6332c 7?? 8mm 3000 units FDG6332C
FDG6332C rev c1 (w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain?source breakdown voltage v gs = 0 v, i d = 250 m a v gs = 0 v, i d = ?250 m a q1 q2 20 ?20 v d bv dss d t j breakdown voltage temperature coefficient i d = 250 m a,ref. to 25 c i d = ?250 m a,ref. to 25 c q1 q2 14 ?14 mv/ c i dss zero gate voltage drain current v ds = 16 v, v gs = 0 v v ds = ?16 v, v gs = 0 v q1 q2 1 ?1 m a i gssf /i gssr gate?body leakage, forward v gs = 12 v, v ds = 0 v 100 na i gssf /i gssr gate?body leakage, reverse v gs = 12v , v ds = 0 v 100 na on characteristics (note 2) v gs( th ) q1 v ds = v gs , i d = 250 m a 0.6 1.1 1.5 gate threshold voltage q2 v ds = v gs , i d = ?250 m a -0.6 ?1.2 ?1.5 v d v gs( th) d t j gate threshold voltage temperature coefficient q1 q2 i d = 250 m a ,ref . to 25 c i d = ?250 m a,ref. to 25 c ?2.8 3 mv/ c r ds(on) q1 v gs = 4.5 v, i d =0.7 a v gs = 2.5 v, i d =0.6 a v gs = 4.5 v, i d =0.7a,t j =125 c 180 293 247 300 400 442 static drain?source on?resistance q2 v g s = ?4.5 v, i d = ?0.6 a v gs = ?2.5 v, i d = ?0.5 a v gs =?4.5 v, i d =?0.6 a,t j =125 c 300 470 400 420 630 700 m w g fs q1 v ds = 5 v i d = 0.7 a 2.8 forward transconductance q2 v ds = ?5 v i d = ?0.6a 1.8 s i d(on) q1 v gs = 4.5 v, v ds = 5 v 1 on?state drain current q2 v gs = ?4.5 v, v ds = ?5 v ?2 a dynamic characteristics c iss q1 v ds =10 v, v gs = 0 v, f=1.0mhz 113 input capacitance q2 v ds =?10 v, v gs = 0 v, f=1.0mhz 114 pf c oss q1 v ds =10 v, v gs = 0 v, f=1.0mhz 34 output capacitance q2 v ds =?10 v, v gs = 0 v, f=1.0mhz 24 pf c rss q1 v ds =10 v, v gs = 0 v, f=1.0mhz 16 reverse transfer capacitance q2 v ds =?10 v, v gs = 0 v, f=1.0mhz 9 pf switching characteristics (note 2) t d(on) q1 5 10 turn?on delay time q2 5.5 11 ns t r q1 7 15 turn?on rise time q2 14 25 ns t d(off) q1 9 18 turn?off delay time q2 6 12 ns t f q1 1.5 3 turn?off fall time q2 for q1 : v ds =10 v, i d = 1 a v g s = 4.5 v, r gen = 6 w for q2 : v ds =?10 v, i d = ?1 a v gs = ?4.5 v, r gen = 6 w 1.7 3.4 ns q g q1 1.1 1.5 total gate charge q2 1.4 2 nc q gs q1 0.24 gate?source charge q2 0.3 nc q gd q1 0.3 gate?drain charge q2 for q1 : v ds =10 v, i d = 0.7 a v gs = 4.5 v, r gen = 6 w for q2 : v ds =?10 v, i d = ?0.6 a v gs = ?4.5 v, r gen = 6 w 0.4 nc FDG6332C
FDG6332C rev c1 (w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units drain?source diode characteristics and maximum ratings i s q1 0.25 maximum continuous drain?source diode forward current q2 ?0.25 a v sd q1 v gs = 0 v, i s = 0.25 a (note 2) 0.74 1.2 drain?source diode forward voltage q2 v gs = 0 v, i s = ?0.25 a (note 2) ?0.77 ?1.2 v notes: 1. r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r q jc is guaranteed by design while r q ja is determined by the user's board design. r q ja = 415c/w when mounted on a minimum pad of fr-4 pcb in a still air environment. 2. pulse test: pulse width < 300 m s, duty cycle < 2.0% FDG6332C
FDG6332C rev c1 (w) typical characteristics: n-channel 0 1 2 3 4 0 1 2 3 4 v ds , drain-source voltage (v) i d , drain current (a) 2.0v 3.0v v gs =4.5v 2.5v 3.5v 0.8 1 1.2 1.4 1.6 1.8 0 1 2 3 4 i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = 2.5v 3.0v 4.0v 3.5v 4.5v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d =0.7a v gs = 4.5v 0 0.2 0.4 0.6 0.8 1 2 3 4 5 v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d =0.4a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 3 v gs , gate to source voltage (v) i d , drain current (a) t a = -55 o c 25 o c 125 o c v ds = 5v 0.0001 0.001 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 1 1.2 v sd , body diode forward voltage (v) i s , reverse drain current (a) t a = 125 o c 25 o c -55 o c v gs = 0v figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. fdg63 3 2c
FDG6332C rev c1 (w) typical characteristics: n-channel 0 1 2 3 4 5 0 0.4 0.8 1.2 1.6 q g , gate charge (nc) v gs , gate-source voltage (v) i d = 0.7a v ds = 5v 15v 10v 0 50 100 150 200 0 5 10 15 20 v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 0.1 1 10 100 v ds , drain-source voltage (v) i d , drain current (a) dc 1s 100ms 100 m s r ds(on) limit v gs = 4.5v single pulse r q ja = 415 o c/w t a = 25 o c 10ms 1ms 0 2 4 6 8 10 0.001 0.01 0.1 1 10 100 t 1 , time (sec) p(pk), peak transient power (w) single pulse r q ja = 415c/w t a = 25c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. fdg633 2c
FDG6332C rev c1 (w) typical characteristics: p-channel 0 0.4 0.8 1.2 1.6 2 0 1 2 3 4 -v ds , drain-source voltage (v) -i d , drain current (a) -3.5v -2.5v -2.0v v gs = -4.5v -3.0v 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = -2.5v -3.0v -3.5v -4.5v -4.0v figure 11. on-region characteristics. figure 12. on-resistance variation with drain current and gate voltage. 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = -0.6a v gs = -4.5v 0.2 0.4 0.6 0.8 1 1.2 1 2 3 4 5 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -0.3 a t a = 125 o c t a = 25 o c figure 13. on-resistance variation with temperature. figure 14. on-resistance variation with gate-to-source voltage. 0 0.5 1 1.5 2 0.5 1 1.5 2 2.5 3 -v gs , gate to source voltage (v) -i d , drain current (a) t a = -55 o c 25 o c 125 o c v ds = -5v 0.0001 0.001 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 1 1.2 -v sd , body diode forward voltage (v) -i s , reverse drain current (a) t a = 125 o c 25 o c -55 o c v gs = 0v figure 15. transfer characteristics. figure 16. body diode forward voltage variation with source current and temperature. fdg63 3 2c
FDG6332C rev c1 (w) typical characteristics : p-channel 0 1 2 3 4 5 0 0.3 0.6 0.9 1.2 1.5 1.8 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -0.6a v ds = -5v -15v -10v 0 40 80 120 160 0 5 10 15 20 -v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 17. gate charge characteristics. figure 18. capacitance characteristics. 0.01 0.1 1 10 0.1 1 10 100 -v ds , drain-source voltage (v) -i d , drain current (a) dc 1s 100ms 10ms 1ms 100 m s r ds(on) limit v gs = -4.5v single pulse r q ja = 415 o c/w t a = 25 o c 0 2 4 6 8 10 0.001 0.01 0.1 1 10 100 single pulse time (sec) power (w) single pulse r q ja = 415 o c/w t a = 25 o c figure 19. maximum safe operating area. figure 20. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 t 1 , time (sec) r(t), normalized effective transient thermal resistance r q ja (t) = r(t) * r q ja r q ja = 415 c/w t j - t a = p * r q ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 21. transient thermal response curve. thermal characterization performed using the conditions described in note 1. transient thermal response will change depending on the circuit board design. fdg633 2c
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